Advanced HDL Synthesis and SOC Prototyping
-15%
portes grátis
Advanced HDL Synthesis and SOC Prototyping
RTL Design Using Verilog
Taraate, Vaibbhav
Springer Verlag, Singapore
01/2019
307
Dura
Inglês
9789811087752
15 a 20 dias
664
Descrição não disponível.
Introduction.- SOC Design.- RTL Design Guidelines.- RTL Design and Verification.- Processor cores and Architecture design.- Buses and protocols in SOC designs.- DSP Algorithms and Video Processing.- ASIC and FPGA Synthesis.- Static Timing Analysis.- SOC Prototyping.- SOC Prototyping guidelines.- Design Integration and SOC synthesis.- Interconnect delays and Timing.- SOC Prototyping and debug techniques.- Testing at the board level.
Este título pertence ao(s) assunto(s) indicados(s). Para ver outros títulos clique no assunto desejado.
FPGA;SOC System Level Verification;ASIC Prototyping;STA scripts;SOC Synthesis
Introduction.- SOC Design.- RTL Design Guidelines.- RTL Design and Verification.- Processor cores and Architecture design.- Buses and protocols in SOC designs.- DSP Algorithms and Video Processing.- ASIC and FPGA Synthesis.- Static Timing Analysis.- SOC Prototyping.- SOC Prototyping guidelines.- Design Integration and SOC synthesis.- Interconnect delays and Timing.- SOC Prototyping and debug techniques.- Testing at the board level.
Este título pertence ao(s) assunto(s) indicados(s). Para ver outros títulos clique no assunto desejado.
